This document is relevant for: Inf1, Inf2, Trn1, Trn2, Trn3

neuron_driver_shared.h#

Shared definitions between Neuron driver and runtime.

Source: src/libnrt/include/ndl/neuron_driver_shared.h

Enumerations#

neuron_driver_feature_flag#

enum neuron_driver_feature_flag {
    NEURON_DRIVER_FEATURE_DMABUF = 1ull << 0,
    NEURON_DRIVER_FEATURE_ASYNC_DMA = 1ull << 1,
    NEURON_DRIVER_FEATURE_BATCH_DMAQ_INIT = 1ull << 2,
    NEURON_DRIVER_FEATURE_BIG_CORE_MAPS = 1ull << 3,
    NEURON_DRIVER_FEATURE_MEM_ALLOC_TYPE = 1ull << 4,
    NEURON_DRIVER_FEATURE_HBM_SCRUB = 1ull << 5,
    NEURON_DRIVER_FEATURE_MEM_ALLOC64 = 1ull << 6,
    NEURON_DRIVER_FEATURE_CONTIGUOUS_SCRATCHPAD = 1ull << 7,
    NEURON_DRIVER_FEATURE_ZEROCOPY = 1ull << 8,
};

Feature flags for driver capabilities.

Source: neuron_driver_shared.h:11

neuron_pod_ctrl_req#

enum neuron_pod_ctrl_req {
    NEURON_NPE_POD_CTRL_REQ_POD = 0,
    NEURON_NPE_POD_CTRL_REQ_SINGLE_NODE = 1,
    NEURON_NPE_POD_CTRL_REQ_KILL = 2,
    NEURON_NPE_POD_CTRL_SET_MODE = 3,
};

Pod control request types.

Source: neuron_driver_shared.h:40

neuron_ultraserver_mode#

enum neuron_ultraserver_mode {
    NEURON_ULTRASERVER_MODE_UNSET = 0,
    NEURON_ULTRASERVER_MODE_X4 = 1,
    NEURON_ULTRASERVER_MODE_X2H = 2,
    NEURON_ULTRASERVER_MODE_X2V = 3,
    NEURON_ULTRASERVER_MODE_X1 = 4,
};

Ultraserver configuration modes.

Source: neuron_driver_shared.h:47

neuron_dma_queue_type#

enum neuron_dma_queue_type {
    NEURON_DMA_QUEUE_TYPE_TX = 0,
    NEURON_DMA_QUEUE_TYPE_RX,
    NEURON_DMA_QUEUE_TYPE_COMPLETION,
};

DMA queue types.

Source: neuron_driver_shared.h:63

NQ_DEVICE_TYPE#

enum NQ_DEVICE_TYPE {
    NQ_DEVICE_TYPE_NEURON_CORE = 0,
    NQ_DEVICE_TYPE_TOPSP,
    NQ_DEVICE_TYPE_MAX
};

Notification queue device types.

Source: neuron_driver_shared.h:115

NQ_TYPE#

enum NQ_TYPE {
    NQ_TYPE_TRACE = 0,
    NQ_TYPE_NOTIFY,
    NQ_TYPE_EVENT,
    NQ_TYPE_ERROR,
    NQ_TYPE_TRACE_DMA,
    NQ_TYPE_THROTTLE,
    NQ_TYPE_MAX
};

Notification queue types.

Source: neuron_driver_shared.h:123

mem_alloc_category_t#

typedef enum {
    NEURON_MEMALLOC_TYPE_UNKNOWN_HOST,
    NEURON_MEMALLOC_TYPE_CODE_HOST,
    NEURON_MEMALLOC_TYPE_TENSORS_HOST,
    NEURON_MEMALLOC_TYPE_CONSTANTS_HOST,
    NEURON_MEMALLOC_TYPE_MISC_HOST,
    NEURON_MEMALLOC_TYPE_NCDEV_HOST,
    NEURON_MEMALLOC_TYPE_NOTIFICATION_HOST,
    NEURON_MEMALLOC_TYPE_UNKNOWN_DEVICE,
    NEURON_MEMALLOC_TYPE_CODE_DEVICE,
    NEURON_MEMALLOC_TYPE_TENSORS_DEVICE,
    NEURON_MEMALLOC_TYPE_CONSTANTS_DEVICE,
    NEURON_MEMALLOC_TYPE_SCRATCHPAD_DEVICE,
    NEURON_MEMALLOC_TYPE_MISC_DEVICE,
    NEURON_MEMALLOC_TYPE_NCDEV_DEVICE,
    NEURON_MEMALLOC_TYPE_COLLECTIVES_DEVICE,
    NEURON_MEMALLOC_TYPE_SCRATCHPAD_NONSHARED_DEVICE,
    NEURON_MEMALLOC_TYPE_NOTIFICATION_DEVICE,
    NEURON_MEMALLOC_TYPE_DMA_RINGS_HOST,
    NEURON_MEMALLOC_TYPE_DMA_RINGS_DEVICE,
    NEURON_MEMALLOC_TYPE_CONTIGUOUS_SCRATCHPAD_DEVICE,
    NEURON_MEMALLOC_TYPE_MAX
} mem_alloc_category_t;

Memory allocation categories for sysfs counters.

Source: neuron_driver_shared.h:234

Structures#

neuron_dma_eng_state#

struct neuron_dma_eng_state {
    __u32 revision_id;
    __u32 max_queues;
    __u32 num_queues;
    __u32 tx_state;
    __u32 rx_state;
};

DMA engine state information.

Source: neuron_driver_shared.h:76

neuron_dma_queue_state#

struct neuron_dma_queue_state {
    __u32 hw_status;
    __u32 sw_status;
    __u64 base_addr;
    __u32 length;
    __u32 head_pointer;
    __u32 tail_pointer;
    __u64 completion_base_addr;
    __u32 completion_head;
};

DMA queue state information.

Source: neuron_driver_shared.h:84

neuron_uuid#

struct neuron_uuid {
    __u8 value[32];
};

UUID structure for model identification.

Source: neuron_driver_shared.h:163

neuron_app_info#

struct neuron_app_info {
    __s32 pid;
    __u8 nc_lock_map;
    struct neuron_uuid uuid_data[APP_INFO_MAX_MODELS_PER_DEVICE];
    size_t host_mem_size;
    size_t device_mem_size;
};

Application information including PID, locked neuron cores, and memory usage.

Source: neuron_driver_shared.h:175

neuron_memcpy_batch_t#

typedef struct neuron_memcpy_batch {
    __u64 mem_handle;
    __u64 mem_handle_offset;
    const nrt_tensor_batch_op_t *ops_ptr;
    __u32 num_ops;
    __u16 bar4_wr_threshold;
    __u16 flags;
    void *context;
} neuron_memcpy_batch_t;

A batch of copy operations for efficient data transfer.

Source: neuron_driver_shared.h:220

nds_header_t#

typedef struct nds_header {
    char signature[4];
    int version;
} nds_header_t;

Neuron Datastore header structure.

Source: neuron_driver_shared.h:330

Constants#

NEURON_DMA_H2T_DEFAULT_QID#

#define NEURON_DMA_H2T_DEFAULT_QID (-1)

H2T DMA Default Queue id.

Source: neuron_driver_shared.h:108

NEURON_MAX_PROCESS_PER_DEVICE#

#define NEURON_MAX_PROCESS_PER_DEVICE 16

Maximum processes per device.

Source: neuron_driver_shared.h:167

NDS_MAX_NEURONCORE_COUNT#

#define NDS_MAX_NEURONCORE_COUNT (4)

Maximum neuron core count for NDS.

Source: neuron_driver_shared.h:323