This document is relevant for: Trn2, Trn3
vLLM Neuron Plugin (Beta) Documentation#
The vLLM Neuron plugin brings the full vLLM serving stack to AWS Trainium
accelerators. It supports continuous batching, speculative decoding
(EAGLE3), disaggregated inference, structured outputs, multimodal models, and
more — all accessible through the standard vllm serve command and
OpenAI-compatible API.
For a high-level overview of inference on Neuron and help choosing the right inference solution, see Inference on Neuron. The source code for the vLLM Neuron plugin is hosted in the vLLM Neuron GitHub repository.
Get started#
Deploy & serve#
Model Recipes#
Tutorials#
Model development#
Concepts & architecture#
Parallelism#
Topic |
Description |
|---|---|
Sharding Q/O weights across DP groups |
|
Per-component independent sharding |
|
Data parallelism overview |
|
KV cache sequence sharding for long contexts |
|
Expert parallelism for MoE |
|
Tensor parallelism overview |
|
Independent TP/DP for vision encoders |
Speculation#
Topic |
Description |
|---|---|
EAGLE3 internals on Neuron |
Multimodal#
Topic |
Description |
|---|---|
FFD block packing for multi-image attention efficiency |
|
Block-based on-device cache for vision encoder outputs |
|
Spatial position embeddings for VLMs |
vLLM integration#
Topic |
Description |
|---|---|
Plugin registration, scheduler, KV cache |
|
KV cache integration points with vLLM |
|
Additional configuration options |
|
Async scheduling and execution design |
|
Reducing decode HBM reads |
|
Available memory determination |
|
FP8 KV cache mechanics |
|
Production metrics design |
|
Profiling integration |
|
Holdback queue and admission control |
|
Block KV cache architecture |
|
Prefill segmentation and KV reuse |
|
Pooling model execution on Neuron |
|
Prompt embedding support |
|
JSON, regex, grammar-constrained generation |
|
DI architecture, NIXL transport, hybrid TP, DCP |
Framework#
Topic |
Description |
|---|---|
Async execution double buffering |
|
Weight loading with parallelism |
|
Model bringup workflow |
|
Model registry and factory pattern |
Compilation#
Topic |
Description |
|---|---|
Compilation cache (hit/miss, remote store) |
|
Ahead-of-time CPU compilation (NEFF extraction) |
|
FX passes architecture |
|
Aliasing output rewrite pass |
|
Device rewriting FX pass |
|
Inplace to out-of-place rewrite |
Accuracy#
Topic |
Description |
|---|---|
Accuracy debugging framework |
|
KV cache analysis |
|
Logit validation |
|
Module test guidelines |
|
Tensor capture |
|
Tensor compare |
|
Tensor replacement |
This document is relevant for: Trn2, Trn3