This document is relevant for: Trn2, Trn3
vLLM integration#
Design documentation for how vLLM Neuron integrates with the vLLM core framework. For user-facing configuration, see the features guide and configuration options.
Topic |
Description |
|---|---|
Plugin registration, scheduler, KV cache |
|
KV cache integration points with vLLM |
|
Additional configuration options |
|
Async scheduling and execution design |
|
Reducing decode HBM reads |
|
Available memory determination |
|
FP8 KV cache mechanics |
|
Production metrics design |
|
Profiling integration |
|
Holdback queue and admission control |
|
Block KV cache architecture |
|
Prefill segmentation and KV reuse |
|
Pooling model execution on Neuron |
|
Prompt embedding support |
|
JSON, regex, grammar-constrained generation |
|
DI architecture, NIXL transport, hybrid TP, DCP |
This document is relevant for: Trn2, Trn3